1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, and is suitably applied to, for example, a non-volatile semiconductor memory device including a memory transistor in which data can be written by injecting carriers into a carrier storage region formed in a side wall of a gate electrode side portion.
2. Description of the Related Art
In recent years, the study of non-volatile semiconductor memory devices, which can be easily manufactured by a standard CMOS (Complementary Metal Oxide Semiconductor) process, has been actively conducted. As such non-volatile semiconductor memory devices, there are known an MTP (Multiple Time PROM) in which data can be written a plurality of times, and an OTP (One Time PROM) in which data can be written only once.
As the non-volatile semiconductor memory device of MTP, for example, a non-volatile semiconductor memory device as described in Japanese Patent Laid-Open No. 2007-142398 (hereinafter, JP2007-142398A) is known. The non-volatile semiconductor memory device described in JP2007-142398A includes a carrier storage region in a side wall, and is configured such that data can be written by injecting carriers into the carrier storage region and such that data can be erased by extracting carriers from the carrier storage region.
However, although, in JP2007-142398A, it is disclosed that data can be repeatedly written and erased, it is difficult to actually extract carriers once injected into the carrier storage region in the side wall. Therefore, it is practical that the non-volatile semiconductor memory device described in JP2007-142398A is used as an OTP in which data can be written only once.
Further, in the non-volatile semiconductor memory device described in JP2007-142398A, a voltage of 5 to 7 [V] needs to be applied to a gate electrode, and the like, in order to inject carriers into the carrier storage region in the side wall, and hence the film thickness of the gate insulating film needs to be correspondingly increased, which results in a problem that the cell size is increased. Further, in the non-volatile semiconductor memory device described in JP2007-142398A, since such the high voltage of 5 to 7 [V] needs to be controlled for each bit line, a peripheral transistor for controlling the memory transistor also needs to be formed as a high-voltage element, and hence the gate insulating film of the peripheral transistor also needs to be formed to have a larger film thickness so as to withstand the high voltage of 5 to 7 [V]. This also results in a problem that the size of the entire circuit configuration is increased as compared with a non-volatile semiconductor memory device of an OTP, which can be configured only by a core MOS (for example, 1.5 [V]-MOS).
Accordingly, the present invention has been made in view of the above described circumstances, and an object of the present invention is to propose a non-volatile semiconductor memory device which can reduce the size of the circuit configuration as compared with the conventional device.